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NXP Semiconductors /LPC18xx /MCPWM /CAP_CLR

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Interpret as CAP_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CAP_CLR0)CAP_CLR0 0 (CAP_CLR1)CAP_CLR1 0 (CAP_CLR2)CAP_CLR2 0RESERVED

Description

Capture clear address

Fields

CAP_CLR0

Writing a 1 to this bit clears the CAP0 register.
CAP_CLR1

Writing a 1 to this bit clears the CAP1 register.
CAP_CLR2

Writing a 1 to this bit clears the CAP2 register.
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data